255.verilog文件注释代码头

{ // Place your 全局 snippets here. Each snippet is defined under a snippet name and has a scope, prefix, body and // description. Add comma separated ids of the languages where the snippet is applicable in the scope field. If scope // is left empty or omitted, the snippet gets applied to all languages. The prefix is what is // used to trigger the snippet and the body will be expanded and inserted. Possible variables are: // $1, $2 for tab stops, $0 for the final cursor position, and ${1:label}, ${2:another} for placeholders. // Placeholders with the same ids are connected. // Example: // Print to console: { // scope: javascript,typescript, // prefix: log, // body: [ // console.log($1);, // $2 // ], // description: Log output to console // } Verilog File Header: { prefix: HEA, // 触发关键词输入时按 Tab 自动补全 body: [ // , // File : ${TM_FILENAME}, // Author : X-Z, // Description : , // Created : $CURRENT_YEAR/$CURRENT_MONTH/$CURRENT_DATE--$CURRENT_HOUR:$CURRENT_MINUTE:$CURRENT_SECOND, // Revision : 1.0, // Company : Your Company, // , ], description: Insert Verilog file header } }{ // Place your snippets for verilog here. Each snippet is defined under a snippet name and has a prefix, body and // description. The prefix is what is used to trigger the snippet and the body will be expanded and inserted. Possible variables are: // $1, $2 for tab stops, $0 for the final cursor position, and ${1:label}, ${2:another} for placeholders. Placeholders with the // same ids are connected. // Example: Print to shixu: { prefix: SX, body: [ always (posedge iw_clk)begin, if(iw_rst)begin, $S0 d0;, end, else if() begin, , end, else begin, , end, end, ], description: SX }, Print to zhuangtaiji: { prefix: ZTJ, body: [ localparam IDLE ,, $S0 $S2,, ,, reg [7:0] state_c,state_n;, always (posedge iw_clk)begin, if(iw_rst)begin, state_c IDLE;, end, else begin, state_c state_n; , end, end, , always (*)begin, case(state_c), IDLE:begin, if()begin, state_n ;, end else begin, state_n IDLE; end, end, $S0 :begin, if()begin, state_n ;, end, else begin, ;, end, end, , , default : ;, endcase, end, , always (posedge iw_clk)begin, if(iw_rst)begin, $S0 d0;, end, else if() begin, , end, else begin, , end, end, ], description: SX }, Print to jishuqi: { prefix: JSQ, body: [ reg [:] cnt;, wire add_cnt;, wire end_cnt;, , always (posedge iw_clk)begin, if(iw_rst)begin, cnt d0;, end, else if(add_cnt) begin, if(end_cnt)begin, cnt d0; end, else begin, cnt cnt 1d1;, end, end, else begin, cnt cnt; , end, end, , assign add_cnt 1b1;, assign end_cnt ;, ], description: SX }, Print to head:{ prefix: HEAD, body: [ /**********************************************************************, * file ${TM_FILENAME}, * brief 简要描述模块功能, * version 1.0, * date ${1:YYYY-MM-DD}, * author ${2:X_Z}, * email ${3:your.emailexample.com}, *, * note, * - 模块描述: 详细描述, * - 输入: ${4:input_signals}, * - 输出: ${5:output_signals}, * - 时钟: ${6:clk}, * - 复位: ${7:rst_n} (低有效), *, * history, * Version | Date | Author | Description, * ------- | -------- | --------- | -----------, * 1.0 | ${8:YYYY-MM-DD} | ${2:X_Z} | Initial creation, **********************************************************************/, , timescale 1ns / 1ps, , module ${9:module_name} (, // Clock and Reset, input wire i_clk, // 时钟信号, input wire i_rst_n, // 复位信号 (低有效), , // Inputs, ${10:input_wires}, , // Outputs, ${11:output_wires}, );, , // , // Parameter Definitions, // , ${12:localparam}, , // , // Signal Declarations, // , ${13:reg/wire signals}, , // , // Main Logic, // , ${14:// Your logic here}, , endmodule ], description: Generate Verilog file header and module template } // // You can also restrict snippets to specific files using include/exclude patterns: // Test snippet: { // prefix: test, // body: test($1, () {\n\t$0\n});, // include: [**/*.test.ts, *.spec.ts], // exclude: [**/temp/*.ts], // description: Insert test block // } }