verilog HDLBits刷题[Finite State Machines]“Exams/2014 q3c”---Q3c:FSM logic

1、题目Given the state-assigned table shown below, implement the logic functions Y[0] and z.Present statey[2:0]Next state Y[2:0]Output zx0x1000000001000100110000100100010011001010110001110012、不理解clk有啥作用3、代码module top_module ( input clk, input [2:0] y, input x, output Y0, output z ); parameter A3b000,B3b001,C3b010,D3b011,E3B100; reg [2:0]next_state; always(*)begin case(y) A: next_statex?B:A; B:next_statex?E:B; C:next_statex?B:C; D:next_statex?C:B; E:next_statex?E:D; default:next_stateA; endcase end assign z(yD||yE); assign Y0next_state[0]; endmodule