verilog HDLBits刷题[Finite State Machines]“Fsm serial”---Serial receiver

1、题目In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.2、正确代码module top_module( input clk, input in, input reset, // Synchronous reset output done ); parameter IDEL5d0,START5d1,DATA15d2,DATA25d3,DATA35d4,DATA45d5,DATA55d6,DATA65d7,DATA75d8,DATA85d9,WAIT_STOP5d10,STOP5d11; reg [4:0]state,next_state; always(posedge clk) if(reset) stateIDEL; else statenext_state; always(*)begin case(state) IDEL:next_statein?IDEL:START; START:next_stateDATA1; DATA1:next_stateDATA2; DATA2:next_stateDATA3; DATA3:next_stateDATA4; DATA4:next_stateDATA5; DATA5:next_stateDATA6; DATA6:next_stateDATA7; DATA7:next_stateDATA8; DATA8:next_statein?STOP:WAIT_STOP; WAIT_STOP:next_statein?IDEL:WAIT_STOP; STOP:next_statein?IDEL:START; default:next_stateIDEL; endcase end assign done(stateSTOP); endmodule下面这个代码的问题是如果没找到停止位为1连续的0会直接从START开始。数据结束应该必须得有一个高才能开始起始位module top_module( input clk, input in, input reset, // Synchronous reset output done ); parameter IDEL5d0,START5d1,DATA15d2,DATA25d3,DATA35d4,DATA45d5,DATA55d6,DATA65d7,DATA75d8,DATA85d9,STOP5d10; reg [4:0]state,next_state; always(posedge clk) if(reset) stateIDEL; else statenext_state; always(*)begin case(state) IDEL:next_statein?IDEL:START; START:next_stateDATA1; DATA1:next_stateDATA2; DATA2:next_stateDATA3; DATA3:next_stateDATA4; DATA4:next_stateDATA5; DATA5:next_stateDATA6; DATA6:next_stateDATA7; DATA7:next_stateDATA8; DATA8:next_statein?STOP:IDEL; STOP:next_statein?START:IDEL; default:next_stateIDEL; endcase end assign done(stateSTOP); endmodule